1. Field of the Invention
The present invention relates to a semiconductor device and a display comprising the same, and more particularly, it relates to a semiconductor device employed for capturing a video signal or the like in a display and a display comprising the same.
2. Description of the Prior Art
A circuit having functions of capturing a low amplitude signal with a certain starting signal, level-converting the signal voltage and holding data thereof is known in general. Such a circuit is employed for capturing addresses and data and holding the data in a memory, for example. This circuit is also employed for capturing a video signal and holding data in a liquid crystal display (LAD) or an organic EL (electro luminescence) display. The following description is made with reference to a circuit for capturing a video signal and holding data in an LCD.
An LCD employing a polysilicon TFT (thin-film transistor) is recently increasingly demanded. Following this, reduction of power consumption and attainment of a digital interface are required to an LCD system.
In order to reduce power consumption in the LCD system, efficiency of a power supply circuit must be increased and a driving voltage must be reduced. The polysilicon TFT having higher performance than an amorphous silicon TFT is applied to an LCD and put into practice mainly for a miniature LCD panel. However, the polysilicon TFT having higher performance than the amorphous silicon TFT is still inferior in performance as compared with a single-crystalline silicon transistor formed on the surface of a silicon substrate. In order to obtain a driving current similar to that in a single-crystalline silicon transistor having an operating voltage of about 3 V, therefore, the polysilicon TFT requires a power supply voltage of 12 to 15 V. Therefore, while the power source for a control IC of the LCD is about 3 V, a level conversion circuit is required for converting the voltage to 12 to 15 V.
In general, therefore, a circuit provided in an LCD panel performs level conversion of a voltage while only a 3 V-system signal is input in the LCD panel. The level conversion circuit is so built into the LCD panel that a level-converted high voltage can be applied to only a necessary portion in the panel while supplying a 3 V-system voltage to the remaining portions. Thus, power consumption can be reduced.
The LCD (liquid crystal display) makes bright/dark display by applying a voltage across a liquid crystal material thereby fluctuating the transmittance of the liquid crystal material. In this case, a counter electrode AC driving system is generally employed for AC-driving a second electrode (counter electrode) different from a first electrode of a display pixel subjected to application of video data thereby halving the amplitude of the video data. Thus, the voltage of a video signal can be reduced thereby reducing power consumption of an external IC as well as that in the panel.
Due to the aforementioned reduction of the power consumption, the voltages of a clock signal and the video signal other than that related to the performance of the polysilicon TFT can be reduced.
In general, requirement for digitization (digital interfacing) of treated signals is increased following reduction of the voltage of the video signal and rapid development of the Internet and the digital signal technique. In particular, the analog video signal is hard to treat in view of digitization. In order to digitize video data, a technique of building a DAC (digital-analog converter) into an LCD panel for converting a digital video signal to an analog video signal is proposed.
In consideration of the above, development of a circuit capable of inputting a video signal in an LCD panel with a 3 V-system digital signal as well as capturing the digital signal and level-converting a power supply voltage in the panel is recently started. Such a circuit is disclosed in 2000 IEEE International Solid-State Circuits Conference, announcement No. TA 11.5 (pp. 188-189) or the like, for example.
FIG. 10 is a circuit diagram showing the circuit structure of a conventional video signal capturing circuit disclosed in the aforementioned literature. Referring to FIG. 10, a conventional data capturing part 101 includes two p-channel transistors PT101 and PT102 and two n-channel transistors NT101 and NT102. Either the source terminals or the drain terminals of the p-channel transistors PT101 and PT102 are connected to a power supply voltage VDD through a switch SW3. The other one of the source terminal and the drain terminal of the p-channel transistor PT101 is connected to either the source terminal or the drain terminal of the n-channel transistor 101. The other one of the source terminal and the drain terminal of the n-channel transistor NT101 is connected to a ground potential GND. The gate terminals of the p-channel transistor PT101 and the n-channel transistor NT101 are connected to a data line Data through a switch SW1.
The other one of the source terminal and the drain terminal of the p-channel transistor PT102 is connected to either the source terminal or the drain terminal of the n-channel transistor NT102. The other one of the source terminal and the drain terminal of the n-channel transistor NT102 is connected to the ground potential GND. The gate terminals of the p-channel transistor PT102 and the n-channel transistor NT102 are connected to an inverted data line /Data through a switch SW2.
The conventional data capturing part 101 having the aforementioned structure has three functions, i.e., a data sensing function of determining data, a function of level-converting a power source and a function of latching captured data. The switches SW1 and SW2 have functions of starting capturing data by entering ON states in synchronization with a sampling pulse. The switch SW3 has a function of entering an OFF state in synchronization with the sampling pulse for stopping charge supply to the data capturing part 101 from the power source (VDD) in data capturing. Two inverter circuits 131 and 132 of an output stage have functions of waveform-shaping captured data and transmitting signals to a subsequent stage.
FIG. 11 illustrates operation timings and operation waveforms of the conventional video signal capturing circuit shown in FIG. 10. The operations of the conventional video signal capturing circuit are now described with reference to FIGS. 10 and 11.
First, a start signal (not shown in FIG. 10) indicating operation initiation of a display panel of an LCD itself goes high, as shown in FIG. 11. Thus, a signal STH indicating starting of a horizontal driving circuit goes high. According to generation of this signal STH, the sampling pulse for capturing video data Data and /Data goes high in synchronization with horizontal basic clocks HCK1 and HCK2. Thus, the switches SW1 and SW2 enter ON states while the switch SW3 enters an OFF state. Therefore, data is input in the data capturing part 101 while cutting off the power source VDD from the data capturing part 101.
The data capturing part 101 determines the data. When the data capturing part 101 completely determines the data and nodes A and B reach voltages corresponding to the video data Data and /Data, the switch SW3 enters an ON state. Thus, the data capturing part 101 and the power source VDD are connected with each other for defining the captured data, level-converting voltages and holding the data.
In the conventional video signal capturing circuit shown in FIG. 10, however, the data capturing part 101 is cut off from the power source VDD (9 V) when capturing and determining the data, and hence the circuit operation of the data capturing part 101 may be unstable. In this case, it may disadvantageously be difficult to stably capture, determine and hold the data. In the conventional video signal capturing circuit shown in FIG. 10, further, the data capturing part 101 has a symmetrical circuit structure with respect to the input data, and hence the degree of freedom in layout is so small that the layout area cannot be satisfactorily minimized.